Verilog by Example

Verilog by Example: A Concise Introduction for FPGA Design
Author: Blaine Readler ID: 0983497303

Paperback: 124 pagesPublisher: Full Arc Press (April 19, 2011)Language: EnglishISBN-10: 0983497303ISBN-13: 978-0983497301 Product Dimensions: 6 x 0.3 x 9 inches Shipping Weight: 6.4 ounces (View shipping rates and policies) Best Sellers Rank: #37,193 in Books (See Top 100 in Books) #71 in Books > Textbooks > Engineering #632 in Books > Engineering & Transportation > Engineering #9158 in Books > reference
I know exactly who this book is for (me, among others, about 15 years ago), but I’m still not sure how to describe it. Thar reader is fluent enough with normal programming languages that bits of syntax won’t be a problem – making it that much easier to address the problematic parallelism implicit in HDLs. That reader also has a fair understanding about the bits & bobs of logic design: gates, RAMs, registers, and the like, but maybe never took the second course in logic design.

This book, a companion to Readler’s "VHDL by example," gives the novice a running start at the other major hardware design language. People on both sides can get pretty het up about which is The One, often along geographic lines (Europe vs. US, East coast vs. West coast). The fact is, though, that you don’t often get to pick. Your employer, your work group or client, the tools and libraries available to you will often make the choice for you. So, it’s best to know both, and Readler’s books treat them with a reasonably even hand.

In the unlikely event that you’re free to choose, it’s a matter of taste. I certainly have my preferences, but they don’t matter much. Verilog reminds a programmer of C – I mean, K&R C, from way back, with all the good and bad that implies. Include files, scopeless macro definition, and uninformative module (or function) prototypes will all look familiar. VHDL, on the other hand, derives consciously from Ada, with all the good and bad that implies. That includes packages (which no one uses), operator overloads (which no one thinks they use, but do), and draconian type checking – something that will cost you a lot of time, but very likely save you even more.

Like its VHDL twin, this gives only the basics, i.e.
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